Invention Application
US20140013171A1 INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES 审中-公开
集成缺陷检测和位置系统和半导体芯片设备的方法

  • Patent Title: INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES
  • Patent Title (中): 集成缺陷检测和位置系统和半导体芯片设备的方法
  • Application No.: US13541063
    Application Date: 2012-07-03
  • Publication No.: US20140013171A1
    Publication Date: 2014-01-09
  • Inventor: Cheow Guan LimGiovanni Ferrara
  • Applicant: Cheow Guan LimGiovanni Ferrara
  • Main IPC: G01R31/3177
  • IPC: G01R31/3177
INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES
Abstract:
Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.
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