A dual mode frequency synthesizer circuit including: a DDS or PLL (204) for receiving an input clock (202) and generating an output clock (206), in a high resolution mode; and an RF switch (210) having its output (208) coupled to the output of the DDS or PLL, a first input (216) for receiving a first injection low phase-noise clock (F1), a second input (218) for receiving a second injection low phase-noise clock (F2), and a control input (222) for selecting one of the first or second injection low phase-noise clocks for a low phase-noise mode.