A sub-threshold voltage circuit of multi-channel length includes a plurality of logic gates, which are electrically connected with one another according to a predetermined manner and composed of a plurality of PMOS transistors and a plurality of NMOS transistors. The logic gates form a plurality of signal paths defining at least one key signal path and a plurality of general signal paths respectively. The channel lengths of the logic gates located on the general signal paths each are the minimum channel length of the manufacturing process of the transistor. The logic gate located on the at least one key signal path is an RSCE PMOS or NMOS transistor, the channel length of which is larger than the minimum channel length of the manufacturing process of the transistor to define a maximum channel length. Thus, the performance is enhanced, leakage current is less, and the circuit area keeps proper in degree.