Invention Application
- Patent Title: Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features
- Patent Title (中): 具有相对于光刻特征的节距减小的集成电路
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Application No.: US13530679Application Date: 2012-06-22
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Publication No.: US20120256309A1Publication Date: 2012-10-11
- Inventor: Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
- Applicant: Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
Public/Granted literature
- US08598632B2 Integrated circuit having pitch reduced patterns relative to photoithography features Public/Granted day:2013-12-03
Information query
IPC分类:
