发明申请
- 专利标题: FAULT-TOLERANT UNIT AND METHOD FOR THROUGH-SILICON VIA
- 专利标题(中): 耐腐蚀单元和通过硅的方法
-
申请号: US13236661申请日: 2011-09-20
-
公开(公告)号: US20120248438A1公开(公告)日: 2012-10-04
- 发明人: Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
- 申请人: Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
- 申请人地址: TW Hsinchu
- 专利权人: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- 当前专利权人: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- 当前专利权人地址: TW Hsinchu
- 优先权: TW100120191 20110609
- 主分类号: H01L23/58
- IPC分类号: H01L23/58 ; H01L21/66
摘要:
A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N11 of the first chip and the node N2i of the second chip, wherein 1≦i≦n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.
公开/授权文献
- US09177940B2 Fault-tolerant unit and method for through-silicon via 公开/授权日:2015-11-03
信息查询
IPC分类: