发明申请
US20120061759A1 Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same
有权
极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
- 专利标题： Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same
- 专利标题（中）： 极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
-
申请号： US12882490申请日： 2010-09-15
-
公开(公告)号： US20120061759A1公开(公告)日： 2012-03-15
- 发明人: Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
- 申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/786
- IPC分类号： H01L29/786 ; H01L21/782
摘要：
A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
公开/授权文献
信息查询
IPC分类:
