Systems and methods for preventing parasitic capacitances within liquid crystal displays are provided. A display panel according to an embodiment may include, for example, a pixel with a pixel electrode and a transistor coupled to a gate line. Additionally, the pixel may include a shielding conductor interposed between the pixel electrode and the gate line. The shielding conductor may shield the pixel electrode from a parasitic capacitance with the gate line by causing a parasitic capacitance to form between the gate line and the shielding conductor instead of between the gate line and the pixel electrode.