Invention Application
- Patent Title: Semiconductor wafer structure and multi-chip stack structure
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Application No.: US12856794Application Date: 2010-08-16
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Publication No.: US20110291268A1Publication Date: 2011-12-01
- Inventor: David Wei WANG , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
- Applicant: David Wei WANG , An-Hong Liu , Hsiang-Ming Huang , Yi-Chang Lee
- Priority: TW099117503 20100601
- Main IPC: H01L23/498
- IPC: H01L23/498

Abstract:
A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.
Information query
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