Invention Application
US20110278736A1 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
有权
用于形成3-D FO-WLCSP的垂直互连结构的半导体器件和方法
- Patent Title: Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
- Patent Title (中): 用于形成3-D FO-WLCSP的垂直互连结构的半导体器件和方法
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Application No.: US13191318Application Date: 2011-07-26
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Publication No.: US20110278736A1Publication Date: 2011-11-17
- Inventor: Yaojian Lin , Kang Chen
- Applicant: Yaojian Lin , Kang Chen
- Applicant Address: SG Singapore
- Assignee: STATS CHIPPAC, LTD.
- Current Assignee: STATS CHIPPAC, LTD.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/60 ; H01L21/56
Abstract:
A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.
Public/Granted literature
- US09082806B2 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Public/Granted day:2015-07-14
Information query
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