Invention Application
- Patent Title: BOTTOM GATE THIN FILM TRANSISTOR AND ACTIVE ARRAY SUBSTRATE
- Patent Title (中): 底部薄膜薄膜晶体管和主动阵列基板
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Application No.: US12500609Application Date: 2009-07-10
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Publication No.: US20100270551A1Publication Date: 2010-10-28
- Inventor: Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
- Applicant: Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
- Applicant Address: TW Hsinchu
- Assignee: AU OPTRONICS CORPORATION
- Current Assignee: AU OPTRONICS CORPORATION
- Current Assignee Address: TW Hsinchu
- Priority: TW98113690 20090424
- Main IPC: H01L33/00
- IPC: H01L33/00 ; H01L29/786

Abstract:
A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.
Public/Granted literature
- US08154061B2 Bottom gate thin film transistor and active array substrate Public/Granted day:2012-04-10
Information query
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