Invention Application
US20090309163A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM AND DISCONTINUITY EXTENDING TO UNDERLYING LAYER
审中-公开
用于增强NMOSFET和PMOSFET性能的方法和结构,具有强化膜和延伸到下层的不连续性
- Patent Title: METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM AND DISCONTINUITY EXTENDING TO UNDERLYING LAYER
- Patent Title (中): 用于增强NMOSFET和PMOSFET性能的方法和结构,具有强化膜和延伸到下层的不连续性
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Application No.: US12136970Application Date: 2008-06-11
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Publication No.: US20090309163A1Publication Date: 2009-12-17
- Inventor: Jing Wang , Huilong Zhu
- Applicant: Jing Wang , Huilong Zhu
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/31

Abstract:
A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack. In an exemplary embodiment, the opening may be extended into an underlying layer such as a source/drain region of the shorter gate stack and a bottom thereof silicided such that a contact formed therein exhibits reduced contact resistance.
Information query
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