- 专利标题: CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics
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申请号: US12078643申请日: 2008-04-02
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公开(公告)号: US20080225133A1公开(公告)日: 2008-09-18
- 发明人: Isao Takayanagi , Junichi Nakamura
- 申请人: Isao Takayanagi , Junichi Nakamura
- 主分类号: H04N5/228
- IPC分类号: H04N5/228 ; H04N5/335
摘要:
An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.
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