发明申请
US20080064214A1 SEMICONDUCTOR PROCESSING INCLUDING ETCHED LAYER PASSIVATION USING SELF-ASSEMBLED MONOLAYER
审中-公开
包括使用自组装单层的蚀刻层钝化的半导体处理
- 专利标题: SEMICONDUCTOR PROCESSING INCLUDING ETCHED LAYER PASSIVATION USING SELF-ASSEMBLED MONOLAYER
- 专利标题(中): 包括使用自组装单层的蚀刻层钝化的半导体处理
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申请号: US11531418申请日: 2006-09-13
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公开(公告)号: US20080064214A1公开(公告)日: 2008-03-13
- 发明人: Taejoon Han , Sang-Jun Cho , Sung-Jin Cho , Tom Choi , Prabhakara Gopaladasu , Sean Kang
- 申请人: Taejoon Han , Sang-Jun Cho , Sung-Jin Cho , Tom Choi , Prabhakara Gopaladasu , Sean Kang
- 申请人地址: US CA Fremont
- 专利权人: LAM RESEARCH CORPORATION
- 当前专利权人: LAM RESEARCH CORPORATION
- 当前专利权人地址: US CA Fremont
- 主分类号: H01L21/311
- IPC分类号: H01L21/311 ; H01L21/461
摘要:
In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.
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