Invention Application
US20070015324A1 Fabrication method for single and dual gate spacers on a semiconductor device
有权
在半导体器件上的单栅极和双栅极间隔物的制造方法
- Patent Title: Fabrication method for single and dual gate spacers on a semiconductor device
- Patent Title (中): 在半导体器件上的单栅极和双栅极间隔物的制造方法
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Application No.: US11217369Application Date: 2005-09-02
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Publication No.: US20070015324A1Publication Date: 2007-01-18
- Inventor: Chao-Hsi Chung , Chu-Chun Hu , Chih-Cheng Wang
- Applicant: Chao-Hsi Chung , Chu-Chun Hu , Chih-Cheng Wang
- Assignee: ProMOS Technologies Inc.
- Current Assignee: ProMOS Technologies Inc.
- Priority: TW94123538 20050712
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/336

Abstract:
A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.
Public/Granted literature
- US07354837B2 Fabrication method for single and dual gate spacers on a semiconductor device Public/Granted day:2008-04-08
Information query
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