Invention Application
- Patent Title: Type-II All-Digital Phase-Locked Loop (PLL)
- Patent Title (中): II型全数字锁相环(PLL)
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Application No.: US11464420Application Date: 2006-08-14
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Publication No.: US20060290435A1Publication Date: 2006-12-28
- Inventor: Robert Staszewski , Dirk Leipold , Khurram Muhammad
- Applicant: Robert Staszewski , Dirk Leipold , Khurram Muhammad
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
Public/Granted literature
- US07382200B2 Type-II all-digital phase-locked loop (PLL) Public/Granted day:2008-06-03
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