发明申请
US20050278567A1 Redundant processing architecture for single fault tolerance 有权
用于单容错的冗余处理架构

Redundant processing architecture for single fault tolerance
摘要:
An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.
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