A phase locked loop (PLL) circuit provides ac devices, such as power inverters and power measurement devices, with a reliable means for synchronizing to ac electrical systems. In an exemplary embodiment, the PLL circuit is configured for operation with single-phase electrical systems and offers substantial noise immunity by basing its locking operations on measured fundamental components, i.e., measured x-y phasors, of the electrical system voltage. Further, with its phasor-based locking operations and with its timer/counter-based operation, the PLL circuit can be implemented partly or wholly in digital processing logic.