Invention Application
- Patent Title: Silicon annealed wafer and silicon epitaxial wafer
- Patent Title (中): 硅退火晶片和硅外延晶片
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Application No.: US10809712Application Date: 2004-03-26
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Publication No.: US20040194692A1Publication Date: 2004-10-07
- Inventor: Hideshi Nishikawa , Nobumitsu Takase , Kazuyuki Egashira , Hiroshi Hayakawa
- Priority: JP2003-097665 20030401
- Main IPC: C30B015/00
- IPC: C30B015/00 ; C30B021/06 ; C30B027/02 ; C30B028/14 ; C30B025/00 ; C30B028/10 ; C30B028/12 ; C30B023/00 ; C30B030/04

Abstract:
A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1null1014 atoms/cm3, COP defects having a size of 0.1 nullm or less in the highest frequency of occurrence and no COP defects having a size of 0.2 nullm or more, oxygen precipitates at a density of 1null104 counts/cm2 or more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1null1014 atoms/cm3, employing the Czochralski method. Moreover, a silicon epitaxial wafer having very small defects and a uniform BMD distribution in the inside can be formed by growing an epitaxial layer on the surface of either the first type base material wafer or the second type base material wafer. Both the silicon annealed wafer and the silicon epitaxial wafer greatly reduce the rate of producing defective devices, thereby enabling the device productivity to be enhanced.
Public/Granted literature
- US07273647B2 Silicon annealed wafer and silicon epitaxial wafer Public/Granted day:2007-09-25
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