The present disclosure relates to a solid state imaging device capable of further decreasing a chip size, a solid state imaging device manufacturing method, and an electronic apparatus. A solid state imaging device includes: a semiconductor substrate with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with wiring connected to the plurality of pixels; and a support substrate that is bonded to the wiring layer. A plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer, and through-holes are provided at positions corresponding to the plurality of electrode pads in the support substrate. The present technology can be applied to, for example, a back side irradiation type CMOS image sensor of a wafer level CSP.