- 专利标题: Partitioned memory architecture with dual resistor memory elements for in-memory serial processing
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申请号: US18045479申请日: 2022-10-11
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公开(公告)号: US12106804B2公开(公告)日: 2024-10-01
- 发明人: Venkatesh P. Gopinath , Pirooz Parvarandeh
- 申请人: GlobalFoundries U.S. Inc.
- 申请人地址: US NY Malta
- 专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人地址: US NY Malta
- 代理机构: Hoffman Warnick LLC
- 代理商 David Cain
- 主分类号: G11C13/00
- IPC分类号: G11C13/00
摘要:
A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements, each including first and second programmable resistors having inputs connected to an input node and outputs connected to first and second bitlines. In each bank, first and second feedback buffers are connected to the first and second bitlines and first and second output nodes. First and second output nodes of banks in the same column are connected to the same first and second column interconnect lines. The initial bank in each row includes amplifiers connected between the input nodes and memory elements. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.
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