Invention Grant
- Patent Title: Redistribution layer layouts on integrated circuits and methods for manufacturing the same
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Application No.: US16201925Application Date: 2018-11-27
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Publication No.: US12068246B2Publication Date: 2024-08-20
- Inventor: Cheng-Yuan Li , Kuo-Cheng Lee , Yun-Wei Cheng , Yen-Liang Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/00 ; H01L23/522 ; H01L23/544

Abstract:
Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
Public/Granted literature
- US20190109086A1 Semiconductor Device and Method for Fabricating the Same Public/Granted day:2019-04-11
Information query
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