- 专利标题: Receiver, memory and testing method
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申请号: US17652039申请日: 2022-02-22
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公开(公告)号: US12021525B2公开(公告)日: 2024-06-25
- 发明人: Zhiqiang Zhang
- 申请人: CHANGXIN MEMORY TECHNOLOGIES, INC.
- 申请人地址: CN Hefei
- 专利权人: CHANGXIN MEMORY TECHNOLOGIES, INC.
- 当前专利权人: CHANGXIN MEMORY TECHNOLOGIES, INC.
- 当前专利权人地址: CN Anhui
- 代理机构: SYNCODA LLC
- 代理商 Feng Ma
- 优先权: CN 2110808712.6 2021.07.16
- 主分类号: H03K19/018
- IPC分类号: H03K19/018 ; H03F3/45 ; H03K5/08 ; H03K5/24 ; H03K19/0185
摘要:
A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.
公开/授权文献
- US20230019429A1 RECEIVER, MEMORY AND TESTING METHOD 公开/授权日:2023-01-19
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