- 专利标题: Current limiting circuit, display device, and current limiting method
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申请号: US17987273申请日: 2022-11-15
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公开(公告)号: US12020644B2公开(公告)日: 2024-06-25
- 发明人: Toshiyuki Kato
- 申请人: JOLED INC.
- 申请人地址: JP Tokyo
- 专利权人: JDI DESIGN AND DEVELOPMENT G.K.
- 当前专利权人: JDI DESIGN AND DEVELOPMENT G.K.
- 当前专利权人地址: JP Tokyo
- 代理机构: Greenblum & Bernstein, P.L.C.
- 优先权: JP 21192495 2021.11.26
- 主分类号: G09G3/3233
- IPC分类号: G09G3/3233
摘要:
A current limiting circuit includes: a delay circuit that receives a video signal, and outputs a delay signal obtained by delaying the video signal by a time period corresponding to one frame; a calculation circuit that receives the video signal, and calculates a gain by which the delay signal is to be multiplied, based on power consumption of the pixels corresponding to the delay signal and power consumption of the pixels corresponding to the video signal; and a gain multiplication circuit that multiplies the delay signal by the gain.
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