- 专利标题: Circuit for improving linearity and channel compensation of PAM4 receiver analog front end
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申请号: US18248654申请日: 2022-04-18
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公开(公告)号: US11811400B1公开(公告)日: 2023-11-07
- 发明人: Yufeng Yao , Minqing Cai , Haonan Wang , Yunlong Ge , Seung Chul Lee
- 申请人: JOYWELL SEMICONDUCTOR (SHANGHAI) CO., LTD.
- 申请人地址: CN Shanghai
- 专利权人: JOYWELL SEMICONDUCTOR (SHANGHAI) CO., LTD.
- 当前专利权人: JOYWELL SEMICONDUCTOR (SHANGHAI) CO., LTD.
- 当前专利权人地址: CN Shanghai
- 代理机构: HAMRE, SCHUMANN, MUELLER & LARSON, P.C.
- 优先权: CN 2110431596.0 2021.04.21
- 国际申请: PCT/CN2022/087354 2022.04.18
- 国际公布: WO2022/222881A 2022.10.27
- 进入国家日期: 2023-04-11
- 主分类号: H03K19/01
- IPC分类号: H03K19/01 ; H03K19/0185
摘要:
The present invention discloses a circuit for improving linearity and channel compensation of PAM4 receiver analog front end, comprising a first stage and a second stage, the first stage comprising first to twentieth transistors, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors. In the first stage circuit, the ninth and tenth transistors are directly coupled to the ground, eliminating the electrical connection to the bias current source. The Input terminals of the ninth and tenth transistors are coupled to the output signals of the preceding nineteenth and twentieth transistors, so that the ninth and tenth transistors serve as both input pairs and current source transistors. The overall current is limited by the thirteenth and fourteenth transistors, which results in a lower power supply voltage for the first stage consisting of the ninth through fourteenth transistors.
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