Invention Grant
- Patent Title: Stacked via structure disposed on a conductive pillar of a semiconductor die
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Application No.: US17243600Application Date: 2021-04-29
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Publication No.: US11756870B2Publication Date: 2023-09-12
- Inventor: Che-Yu Yeh , Tsung-Shu Lin , Wei-Cheng Wu , Tsung-Yu Chen , Li-Han Hsu , Chien-Fu Tseng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/48 ; H01L25/065 ; H01L23/00

Abstract:
A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
Public/Granted literature
- US20220352060A1 STACKED VIA STRUCTURE Public/Granted day:2022-11-03
Information query
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