- 专利标题: Compiler flow logic for reconfigurable architectures
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申请号: US17326128申请日: 2021-05-20
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公开(公告)号: US11714780B2公开(公告)日: 2023-08-01
- 发明人: David Alan Koeplinger , Raghu Prabhakar , Sumti Jairath
- 申请人: SambaNova Systems, Inc.
- 申请人地址: US CA Palo Alto
- 专利权人: SambaNova Systems, Inc.
- 当前专利权人: SambaNova Systems, Inc.
- 当前专利权人地址: US CA Palo Alto
- 代理机构: Flagship Patents
- 代理商 Sikander Khan; Bruce Young
- 主分类号: G06F15/78
- IPC分类号: G06F15/78 ; G06F16/901 ; G06F8/41 ; G06F12/02
摘要:
The technology disclosed partitions a dataflow graph of a high-level program into memory allocations and execution fragments. The memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph. The execution fragments represent operations on the data. The technology disclosed designates the memory allocations to virtual memory units and the execution fragments to virtual compute units. The technology disclosed partitions the execution fragments into memory fragments and compute fragments, and assigns the memory fragments to the virtual memory units and the compute fragments to the virtual compute units. The technology disclosed then allocates the virtual memory units to physical memory units and the virtual compute units to physical compute units. It then places the physical memory units and the physical compute units onto positions in the array of configurable units and routes data and control networks between the placed positions.
公开/授权文献
- US20210271630A1 Compiler Flow Logic for Reconfigurable Architectures 公开/授权日:2021-09-02
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