- 专利标题: Circuits and methods for a cascade phase locked loop
-
申请号: US17572703申请日: 2022-01-11
-
公开(公告)号: US11595050B2公开(公告)日: 2023-02-28
- 发明人: Tsung-Hsien Tsai , Ruey-Bin Sheen
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Jones Day
- 主分类号: H03L7/099
- IPC分类号: H03L7/099 ; H03L7/081
摘要:
Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal. A delay locked loop receives the middle frequency clock signal and the frequency increasing (UP) signal and delays the middle frequency clock signal based on the frequency increasing (UP) signal to generate the realignment clock signal. The second phase lock loop receives the realignment clock signal and adjusts the phase difference between the output signal and the low frequency reference clock signal based on the realignment clock signal.
公开/授权文献
- US20230013600A1 Circuits and Methods for a Cascade Phase Locked Loop 公开/授权日:2023-01-19
信息查询