- 专利标题： Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability
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申请号： US17097406申请日： 2020-11-13
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公开(公告)号： US11532549B2公开(公告)日： 2022-12-20
- 发明人: Shu-Wei Li , Yu-Chen Chan , Shin-Yi Yang , Ming-Han Lee
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Eschweiler & Potashnik, LLC
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; H01L23/528 ; H01L21/768
摘要：
In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.
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