- 专利标题： Integrated circuit test method and structure thereof
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申请号： US17195537申请日： 2021-03-08
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公开(公告)号： US11532524B2公开(公告)日： 2022-12-20
- 发明人: Hsien-Wen Liu , Hsien-Wei Chen
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L21/66
- IPC分类号： H01L21/66 ; H01L23/00
摘要：
A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
公开/授权文献
- US20220028748A1 INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF 公开/授权日：2022-01-27
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