- 专利标题: Multilayer circuit board manufacturing method
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申请号: US16463552申请日: 2017-11-24
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公开(公告)号: US11527415B2公开(公告)日: 2022-12-13
- 发明人: Yoshinori Matsuura , Tetsuro Sato , Takenori Yanai , Toshimi Nakamura
- 申请人: MITSUI MINING & SMELTING CO., LTD.
- 申请人地址: JP Tokyo
- 专利权人: MITSUI MINING & SMELTING CO., LTD.
- 当前专利权人: MITSUI MINING & SMELTING CO., LTD.
- 当前专利权人地址: JP Tokyo
- 代理机构: Greenblum & Bernstein, P.L.C.
- 优先权: JPJP2016-230539 20161128
- 国际申请: PCT/JP2017/042288 WO 20171124
- 国际公布: WO2018/097264 WO 20180531
- 主分类号: H01L21/48
- IPC分类号: H01L21/48 ; H01L21/683 ; H01L23/498 ; H01L23/31
摘要:
There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
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