- 专利标题: Method, apparatus, system for early page granular hints from a PCIe device
-
申请号: US15721777申请日: 2017-09-30
-
公开(公告)号: US11347662B2公开(公告)日: 2022-05-31
- 发明人: Ishwar Agarwal , Rupin H. Vakharwala , Rajesh M. Sankaran , Stephen R. Van Doren
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Alliance IP, LLC
- 主分类号: G06F13/16
- IPC分类号: G06F13/16 ; G06F12/0862 ; G06F12/1009 ; G06F12/1045 ; G06F13/42
摘要:
Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.
公开/授权文献
信息查询