- 专利标题: Delta-sigma modulator and method of driving delta-sigma modulator
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申请号: US17267944申请日: 2019-09-13
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公开(公告)号: US11245414B2公开(公告)日: 2022-02-08
- 发明人: Takashi Matsumoto
- 申请人: Sony Semiconductor Solutions Corporation
- 申请人地址: JP Kanagawa
- 专利权人: Sony Semiconductor Solutions Corporation
- 当前专利权人: Sony Semiconductor Solutions Corporation
- 当前专利权人地址: JP Kanagawa
- 代理机构: Michael Best & Friedrich LLP
- 优先权: JPJP2018-172034 20180914
- 国际申请: PCT/JP2019/036012 WO 20190913
- 国际公布: WO2020/054830 WO 20200319
- 主分类号: H03M3/00
- IPC分类号: H03M3/00 ; H03M1/06 ; H03M1/74
摘要:
Instability of an internal state in a current-input-type delta-sigma modulator is reduced in a case where input changes sharply.
A signal current is input to a first integration node. A difference current between a fixed current and the signal current is input to a second integration node. A voltage-to-current converter that converts a difference voltage between the voltage of the first integration node and a first reference voltage into a current and outputs it is connected between the first integration node and the second integration node. The voltage of the second integration node is compared with a second reference voltage, and a 1-bit digital signal is output. Current is draws from the first integration node or the second integration node according to the 1-bit digital signal. A short-circuit switch is provided between the first integration node and the second integration node for short-circuiting them.
A signal current is input to a first integration node. A difference current between a fixed current and the signal current is input to a second integration node. A voltage-to-current converter that converts a difference voltage between the voltage of the first integration node and a first reference voltage into a current and outputs it is connected between the first integration node and the second integration node. The voltage of the second integration node is compared with a second reference voltage, and a 1-bit digital signal is output. Current is draws from the first integration node or the second integration node according to the 1-bit digital signal. A short-circuit switch is provided between the first integration node and the second integration node for short-circuiting them.
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