发明授权
- 专利标题: Framing protocol supporting low-latency serial interface in an emulation system
-
申请号: US16217465申请日: 2018-12-12
-
公开(公告)号: US11243856B1公开(公告)日: 2022-02-08
- 发明人: Yuhei Hayashi , Mitchell G. Poplack
- 申请人: CADENCE DESIGN SYSTEMS, INC.
- 申请人地址: US CA San Jose
- 专利权人: CADENCE DESIGN SYSTEMS, INC.
- 当前专利权人: CADENCE DESIGN SYSTEMS, INC.
- 当前专利权人地址: US CA San Jose
- 代理机构: Foley & Lardner LLP
- 主分类号: G06F11/22
- IPC分类号: G06F11/22 ; G06F11/273 ; G06F30/331 ; G06F9/455 ; H04L29/08
摘要:
Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such that the switching ASIC may stop routing data through the SerDes interface during the gap cycles. The start-of-packet molecule may include a start-of-packet word, a status word, cyclic redundancy check word, and an idle word. The end-of-packet molecule may include an end-of-packet word, a status word, a cyclic redundancy check word, and an idle word.
信息查询