- 专利标题: Double clock architecture for small duty cycle DC-DC converter
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申请号: US16559118申请日: 2019-09-03
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公开(公告)号: US11057028B2公开(公告)日: 2021-07-06
- 发明人: Alessandro Bertolini , Alberto Cattani , Stefano Ramorini , Alessandro Gasparini
- 申请人: STMicroelectronics S.r.l.
- 申请人地址: IT Agrate Brianza
- 专利权人: STMicroelectronics S.r.l.
- 当前专利权人: STMicroelectronics S.r.l.
- 当前专利权人地址: IT Agrate Brianza
- 代理机构: Crowe & Dunlevy
- 主分类号: H03K3/017
- IPC分类号: H03K3/017 ; H03K5/04 ; H03K7/08 ; H03K5/156 ; H02M3/158
摘要:
A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
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