- 专利标题: Step height mitigation in resistive random access memory structures
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申请号: US16422207申请日: 2019-05-24
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公开(公告)号: US11038108B2公开(公告)日: 2021-06-15
- 发明人: Wei-Ming Wang , Chia-Wei Liu , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao , Huei-Tzu Wang
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- 主分类号: H01L45/00
- IPC分类号: H01L45/00 ; H01L27/24
摘要:
The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
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