Invention Grant
- Patent Title: Methods, apparatus and system for a local interconnect feature over an active region in a finFET device
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Application No.: US16150026Application Date: 2018-10-02
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Publication No.: US10937693B2Publication Date: 2021-03-02
- Inventor: Ruilong Xie , Andreas Knorr , Haiting Wang , Hui Zang
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L29/66 ; H01L21/285 ; H01L21/02
Abstract:
At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.
Information query
IPC分类:
