- 专利标题: Integrated circuit and layout design method
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申请号: US16282419申请日: 2019-02-22
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公开(公告)号: US10784249B2公开(公告)日: 2020-09-22
- 发明人: Hirokazu Okano
- 申请人: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- 申请人地址: JP Tokyo JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- 当前专利权人: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- 当前专利权人地址: JP Tokyo JP Tokyo
- 代理机构: White & Case LLP
- 优先权: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@6ff32ff6
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H01L27/02 ; G06F30/394
摘要:
According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.
公开/授权文献
- US20200091132A1 INTEGRATED CIRCUIT AND LAYOUT DESIGN METHOD 公开/授权日:2020-03-19
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