发明授权
- 专利标题: Simulation event reduction and power control during MBIST through clock tree management
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申请号: US15936999申请日: 2018-03-27
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公开(公告)号: US10783299B1公开(公告)日: 2020-09-22
- 发明人: Steven Lee Gregor , Puneet Arora , Norman Robert Card
- 申请人: Cadence Design Systems, Inc.
- 申请人地址: US CA San Jose
- 专利权人: CADENCE DESIGN SYSTEMS, INC.
- 当前专利权人: CADENCE DESIGN SYSTEMS, INC.
- 当前专利权人地址: US CA San Jose
- 代理机构: Tarolli, Sundheim, Covell & Tummino LLP
- 主分类号: G06F30/00
- IPC分类号: G06F30/00 ; G06F30/3312 ; G06F111/20 ; G06F119/12
摘要:
An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.
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