A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.