- 专利标题: 3D Chip-on-wager-on-substrate structure with via last process
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申请号: US16221831申请日: 2018-12-17
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公开(公告)号: US10535631B2公开(公告)日: 2020-01-14
- 发明人: Chen-Hua Yu , Ming-Fa Chen , Wen-Ching Tsai , Sung-Feng Yeh
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L23/538 ; H01L23/00 ; H01L21/768 ; H01L23/48 ; H01L21/311
摘要:
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
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