- 专利标题： Warpage control in the packaging of integrated circuits
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申请号： US15380671申请日： 2016-12-15
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公开(公告)号： US10512124B2公开(公告)日： 2019-12-17
- 发明人: Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater Matsil, LLP
- 主分类号： B23K31/02
- IPC分类号： B23K31/02 ; H01L21/00 ; H01L23/00 ; H05B3/02 ; H01L21/677 ; H01L21/683 ; B23K3/08 ; B23K101/40
摘要：
A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
公开/授权文献
- US20170098571A1 Warpage Control in the Packaging of Integrated Circuits 公开/授权日：2017-04-06
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