- 专利标题： Techniques for forming device having etch-resistant isolation oxide
-
申请号： US15901769申请日： 2018-02-21
-
公开(公告)号： US10510870B2公开(公告)日： 2019-12-17
- 发明人: Min Gyu Sung , Sony Varghese , Jae Young Lee , Johannes Van Meer
- 申请人： Varian Semiconductor Equipment Associates, Inc.
- 申请人地址： US MA Gloucester
- 专利权人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
- 当前专利权人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
- 当前专利权人地址： US MA Gloucester
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L29/66 ; H01L21/762 ; H01L21/3115 ; H01L29/06 ; H01L29/08 ; H01L21/306 ; H01L21/265
摘要：
A method for forming a semiconductor device may include providing a transistor structure. The transistor structure may include a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures. The method may include implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins. The altered portion of the isolation layer may have a first etch rate, wherein an unaltered portion of the isolation layer, not exposed to the ions, has a second etch rate, greater than the first etch rate.
公开/授权文献
信息查询
IPC分类:
