Invention Grant
- Patent Title: System for parallelized cognitive signal denoising
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Application No.: US15910922Application Date: 2018-03-02
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Publication No.: US10404299B1Publication Date: 2019-09-03
- Inventor: Peter Petre , Bryan H. Fong , Shankar R. Rao
- Applicant: HRL Laboratories, LLC
- Applicant Address: US CA Malibu
- Assignee: HRL Laboratories, LLC
- Current Assignee: HRL Laboratories, LLC
- Current Assignee Address: US CA Malibu
- Agency: Tope-McKay & Associates
- Main IPC: H04B1/10
- IPC: H04B1/10 ; G06N3/04

Abstract:
Described is a cognitive signal processor (CSP) for signal denoising. In operation, the CSP receives a noisy signal as a time-series of data points from a mixture of both noise and one or more desired waveform signals. The noisy signal is linearly mapped to reservoir states of a dynamical reservoir. A high-dimensional state-space representation is then generated of the noisy signal by combining the noisy signal with the reservoir states. A delay-embedded state signal is generated from the reservoir states. The reservoir states are denoised by removing noise from each reservoir state signal, resulting in a real-time denoised spectrogram of the noisy signal. A denoised waveform signal is generated combining the denoised reservoir states. Additionally, the signal denoising process is implemented in software or digital hardware by converting the state-space representation of the dynamical reservoir to a system of delay difference equations and then applying a linear basis approximation.
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