Invention Grant
- Patent Title: Bump structure having a side recess and semiconductor structure including the same
-
Application No.: US15803008Application Date: 2017-11-03
-
Publication No.: US10388622B2Publication Date: 2019-08-20
- Inventor: Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/00

Abstract:
In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.
Public/Granted literature
- US20180053741A1 BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME Public/Granted day:2018-02-22
Information query
IPC分类: