The present disclosure relates to an array substrate and a display panel. The array substrate includes a plurality of scanning lines and a plurality of data lines intersecting with each other to form a plurality of pixel cells. The pixel cells are divided into the pixel cells within a first area and the pixel cells within a second area along the scanning lines. Each of the pixel cells within the second area includes a first thin film transistor (TFT) and a control unit connected to the first TFT. The control unit is configured to reduce a pixel voltage of the pixel cell where the first TFT is configured. As such, the display panel may display images uniformly, and display performance of the display panel may be improved.