Invention Grant
- Patent Title: Low stress vias
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Application No.: US15597699Application Date: 2017-05-17
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Publication No.: US10283449B2Publication Date: 2019-05-07
- Inventor: Ilyas Mohammed , Belgacem Haba , Cyprian Emeka Uzoh
- Applicant: Tessera, Inc.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/48 ; H01L23/532 ; H01L21/768

Abstract:
A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
Public/Granted literature
- US20170250132A1 LOW STRESS VIAS Public/Granted day:2017-08-31
Information query
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