- 专利标题: Wafer level chip scale packaging intermediate structure apparatus and method
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申请号: US14037185申请日: 2013-09-25
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公开(公告)号: US10269619B2公开(公告)日: 2019-04-23
- 发明人: Chen-Hua Yu , Der-Chyang Yeh
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 主分类号: H05K3/42
- IPC分类号: H05K3/42 ; H05K3/46 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L25/10 ; H01L21/768 ; H01L23/498 ; H01L23/538
摘要:
Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
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