Invention Grant
- Patent Title: Power overlay structure and reconstituted semiconductor wafer having wirebonds
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Application No.: US15472912Application Date: 2017-03-29
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Publication No.: US10204881B2Publication Date: 2019-02-12
- Inventor: Arun Virupaksha Gowda , Paul Alan McConnelee
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/522 ; H01L21/78 ; H01L25/00 ; H01L21/768 ; H01L21/683 ; H01L23/528 ; H01L25/07 ; H01L23/31 ; H01L23/525

Abstract:
A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.
Public/Granted literature
- US20170200692A1 POWER OVERLAY STRUCTURE HAVING WIREBONDS AND METHOD OF MANUFACTURING SAME Public/Granted day:2017-07-13
Information query
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