- 专利标题: Surface finishes for interconnection pads in microelectronic structures
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申请号: US15545670申请日: 2015-02-25
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公开(公告)号: US10121752B2公开(公告)日: 2018-11-06
- 发明人: Srinivas V. Pietambaram , Kyu Oh Lee
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Green, Howard, & Mughal LLP.
- 国际申请: PCT/US2015/017435 WO 20150225
- 国际公布: WO2016/137452 WO 20160901
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; B23K35/26 ; C22C13/00 ; C22C19/03 ; H01L23/498
摘要:
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
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