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发明授权
CN1992073B 地址译码器、存储装置、处理器装置、以及地址译码方法 失效 - 权利终止

地址译码器、存储装置、处理器装置、以及地址译码方法
摘要：
地址译码器、存储装置、处理器装置、以及地址译码方法。地址译码器包括：多个译码单元(13)，各由组合逻辑电路构成；取反电路(16)，对所述译码单元(13)的输出进行取反；“与”电路(14)，在已由所述取反电路(16)取反的所述译码单元(13)的输出信号与所述译码单元(13)的另一个输出信号之间执行逻辑“与”运算。这种布置使得可以简化电路结构、提高处理速度，并减少功耗。
摘要（英）：

The invention relates to an address decoder, storage device, processor device, and address decoding method for the storage device. The address decoder includes: a plurality of decode units (13) each formed by a combinational logic circuit; an inverting circuit (16) which inverts an output of said decode unit (13); an AND circuit (14) which performs a logical AND operation between an output signalof said decode unit (13), which has been inverted by said inverting circuit (16), and another one of said plurality of decode units (13). This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.

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